In order to ensure the highest reliability, semiconductor devices should be designed for reliability. As with DFM (Design for Manufacturing) and DFT (Design for Testing), additional silicon structures are embedded during the IC Design to address reliability aspects of the devices.
The DUT (Device Under Test) is put and simultaneously tested into a stable climatic and electronic environment, where an adequate combination of both thermal and electronic signals (“Adaptive Stress Matrix”) stimulates a wide range of failures modes. Advanced algorithms detect potential failures before they actually fail by picking up signatures of latent defects (e.g. an electric value which starts drifting). Detailed Reliability data from Engineering validation & qualification lots are analyzed to optimize design and process, with the least number of design iterations.
Instead of testing with ATE before and after Burn-In, the test is done during Burn In (TDBI). Reliability data are gathered and analyzed for process improvement. Based on results, the number of hours of TDBI are progressively reduced and replaced by a Process Monitoring with samples taken from production lots.