UNIVERSAL TEST PLATFORM

State of the Art approach to qualify chips for Zero Defect & 100% Yield

POWER

from 0W to >3000W

VOLTAGE

from 0V to 6000V

TEMPERATURE

from - 40°C to +175°C

Customer Benefits

Zero Defect & Zero Scraps

Shorter Time to Market

COO minimization

UNIVERSAL Test Platform

Industry 4.0 readiness

Competitivity

Sustainability

Device Support

SoC
Logic · Mixed-Signal
Multi-die Systems
Mixed-Signal · Power
MEMS
Analog · Mixed-Signal
Memory
NVM Test Chip
Smart Power ICs
Power · Analog
Power SiC & GaN
Power · WBG
Photonics IC
Analog · Mixed-Signal
HPC Multi-die system

TfR tester
Test for Realiability

to combine stress and test in the same insertion.

Configurable by HW kits and SW libraries

to manage different IC families: low/high power SOC, Memories, MEMs, smART Power...

Management of External Test/stress Instruments

(on Fixture BOST IPs) to extend test and stress capabilities for the specific IC family.

Scalable to approach engineering, Reliability and Production tests

with the same platform, development and test environment.