WAFER & PACKAGE LEVEL TEST AND BURN-IN FOR SiC & GaN
WAFER & PACKAGE LEVEL TEST AND BURN-IN FOR SiC & GaN
Augmented Test / stress coverage including Dynamic Gate Stress
Dices stress up to 2,5KV
HTRB, HTGB stress
IDSs, IGSs, Vth, BVDss Measurements
Dynamic Gate stress up to 150KHz
Modular and Scalable Tester Architecture
Full wafer stress and test up to 3.000 dices in parallel
Modular and configurable dices Power Supply subsystem up to 2,5KV
Plug & Play on field reconfiguration
Guaranteed Stress and Test accuracy
Stress not affected by dices different leakage level
Short interconnections to maximize measurement accuracy and dynamic gate stress performances
High power efficiency - «Per die» Tester Architecture
Independent per channel protection of tester electronics/contacts vs in-die
and intra-die issues (i.e. short circuits, arching, ...)
Micropower consumption design
High Parallelism in a Compact Footprint and Volume for minimized COO
Up to 3K dices tested in a compact footprint/volume:
600x750x300mm (W-D-H)
Suitable for compact vertical Test Cell Solutions
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